The driving circuit of liquid crystal displays mainly includes a gate driving circuit and a data driving circuit, wherein the data driving circuit latches the inputted display data timely and orderly, and inputs it to the data line of the liquid crystal panel after converting it into an analog signal; the gate driving circuit converts the inputted clock signal into a turn-on/turn-off voltage via SR (Shift Register) conversion, which turn-on/turn-off voltage is applied onto the gate lines of the liquid crystal panel in sequence. In addition, the shift register in the gate driving circuit is also used for generating a scanning signal in the scanning gate line.
In order to meet the requirement of bidirectional scanning, some bidirectional scanning gate driving circuits are proposed in the prior art. these bidirectional scanning gate driving circuits generally include multi-stage of shift registers, each shift register S/R(n) (1≤n≤N) outputs the scanning signal to a corresponding gate line G(n) through its own output signal output terminal OutPut, and outputs the scanning signal to the reset signal input terminal RESET of the S/R(n−1) and the signal input terminal InPut of the S/R(n+1). The scanning signal plays the functions of resetting and starting to the S/R(n−1) and the S/R(n+1) respectively, wherein S/R(1) inputs a frame start signal STV through its own signal input terminal. The basic principles of the shift registers in these gate driving circuits are all consistent, referring to FIG. 2, which is a structural schematic view of a typical shift register in the bidirectional scanning gate driving circuit. The input part thereof includes two transistors M1 and M2, wherein the gate of M1 is connected with the INPUT (i.e., G(n−1)), the source is connected with the VDD; the gate of M2 is connected with the RESET (i.e., G(n+1)), the source is connected with the VSS; thus in forward scanning, the VDD terminal is inputted with a high electrical level, the VSS terminal is inputted with a low electrical level, the high electrical level pulse of the G(n−1) turns on the transistor M1, to realize charging of the PU point; the high electrical level pulse of the G(n+1) turns on the transistor M2, to realize reset of the PU point; while in backward scanning, the VDD terminal is inputted with a low electrical level, the VSS terminal is inputted with a high electrical level; the high electrical level pulse of the RESET (G(n+1)) turns on the transistor M2, to realize charging of the PU point, the high electrical level pulse of the INPUT (G(n−1)) turns on the transistor M2, to realize reset of the PU point. In this way, backward scanning of the corresponding gate driving circuit can be realized by converting the access voltages of the VDD terminal and the VSS terminal. However, VSS signal lines and VDD signal lines need to be arranged in the gate driving circuit constituted by such shift registers, which increases the layout area of the gate driving circuit, and is unfavorable for narrowing down the frame of the display panel.